{"id":478094,"date":"2023-08-09T09:27:19","date_gmt":"2023-08-09T09:27:19","guid":{"rendered":""},"modified":"2023-09-05T11:16:02","modified_gmt":"2023-09-05T11:16:02","slug":"nand-logic-gate","status":"publish","type":"wiki","link":"https:\/\/oneproxy.pro\/vn\/wiki\/nand-logic-gate\/","title":{"rendered":"C\u1ed5ng logic NAND"},"content":{"rendered":"<p>C\u1ed5ng logic NAND l\u00e0 c\u1ed5ng logic k\u1ef9 thu\u1eadt s\u1ed1 ch\u1ec9 xu\u1ea5t ra sai ho\u1eb7c \u201c0\u201d khi c\u1ea3 hai \u0111\u1ea7u v\u00e0o c\u1ee7a n\u00f3 \u0111\u1ec1u \u0111\u00fang ho\u1eb7c \u201c1\u201d. Trong t\u1ea5t c\u1ea3 c\u00e1c tr\u01b0\u1eddng h\u1ee3p kh\u00e1c, n\u00f3 tr\u1ea3 v\u1ec1 true ho\u1eb7c \u201c1\u201d. Bi\u1ec3u t\u01b0\u1ee3ng v\u00e0 h\u00e0nh vi c\u1ee7a n\u00f3 tr\u00e1i ng\u01b0\u1ee3c v\u1edbi c\u1ed5ng logic AND v\u00e0 l\u00e0 m\u1ed9t trong nh\u1eefng kh\u1ed1i x\u00e2y d\u1ef1ng c\u01a1 b\u1ea3n trong \u0111i\u1ec7n t\u1eed k\u1ef9 thu\u1eadt s\u1ed1.<\/p>\n<h2>L\u1ecbch s\u1eed ngu\u1ed3n g\u1ed1c c\u1ee7a C\u1ed5ng logic NAND v\u00e0 s\u1ef1 \u0111\u1ec1 c\u1eadp \u0111\u1ea7u ti\u00ean v\u1ec1 n\u00f3<\/h2>\n<p>C\u1ed5ng NAND \u0111\u01b0\u1ee3c h\u00ecnh th\u00e0nh l\u1ea7n \u0111\u1ea7u ti\u00ean v\u00e0o \u0111\u1ea7u th\u1ebf k\u1ef7 20, sau s\u1ef1 ph\u00e1t tri\u1ec3n c\u1ee7a c\u1ed5ng AND v\u00e0 OR. Vi\u1ec7c s\u1eed d\u1ee5ng c\u1ed5ng NAND c\u00f3 th\u1ec3 b\u1eaft ngu\u1ed3n t\u1eeb lu\u1eadn v\u0103n th\u1ea1c s\u0129 mang t\u00ednh \u0111\u1ed9t ph\u00e1 n\u0103m 1938 c\u1ee7a Claude Shannon, \u201cPh\u00e2n t\u00edch mang t\u00ednh bi\u1ec3u t\u01b0\u1ee3ng c\u1ee7a m\u1ea1ch chuy\u1ec3n m\u1ea1ch v\u00e0 chuy\u1ec3n m\u1ea1ch\u201d. Shannon \u0111\u00e3 ch\u1ec9 ra r\u1eb1ng b\u1ea5t k\u1ef3 ch\u1ee9c n\u0103ng logic n\u00e0o c\u0169ng c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c th\u1ef1c hi\u1ec7n ch\u1ec9 b\u1eb1ng c\u1ed5ng NAND. Kh\u00e1m ph\u00e1 n\u00e0y \u0111\u00e3 \u0111\u1eb7t n\u1ec1n m\u00f3ng cho l\u00fd thuy\u1ebft thi\u1ebft k\u1ebf m\u1ea1ch k\u1ef9 thu\u1eadt s\u1ed1 v\u00e0 vi\u1ec7c s\u1eed d\u1ee5ng c\u1ed5ng NAND t\u1eeb \u0111\u00f3 \u0111\u00e3 tr\u1edf n\u00ean ph\u1ed5 bi\u1ebfn trong thi\u1ebft b\u1ecb \u0111i\u1ec7n t\u1eed k\u1ef9 thu\u1eadt s\u1ed1.<\/p>\n<h2>Th\u00f4ng tin chi ti\u1ebft v\u1ec1 C\u1ed5ng logic NAND. M\u1edf r\u1ed9ng ch\u1ee7 \u0111\u1ec1 C\u1ed5ng logic NAND<\/h2>\n<p>C\u1ed5ng NAND c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c hi\u1ec3u l\u00e0 s\u1ef1 k\u1ebft h\u1ee3p c\u1ee7a c\u1ed5ng AND theo sau l\u00e0 c\u1ed5ng NOT. N\u00f3 nh\u1eadn hai \u0111\u1ea7u v\u00e0o nh\u1ecb ph\u00e2n v\u00e0 tr\u1ea3 v\u1ec1 m\u1ed9t \u0111\u1ea7u ra nh\u1ecb ph\u00e2n theo b\u1ea3ng ch\u00e2n l\u00fd sau:<\/p>\n<table>\n<thead>\n<tr>\n<th>\u0110\u1ea7u v\u00e0o A<\/th>\n<th>\u0110\u1ea7u v\u00e0o B<\/th>\n<th>\u0111\u1ea7u ra<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>0<\/td>\n<td>0<\/td>\n<td>1<\/td>\n<\/tr>\n<tr>\n<td>0<\/td>\n<td>1<\/td>\n<td>1<\/td>\n<\/tr>\n<tr>\n<td>1<\/td>\n<td>0<\/td>\n<td>1<\/td>\n<\/tr>\n<tr>\n<td>1<\/td>\n<td>1<\/td>\n<td>0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>T\u00ean \u201cNAND\u201d c\u00f3 ngu\u1ed3n g\u1ed1c t\u1eeb \u201cNOT AND.\u201d Trong \u0111\u1ea1i s\u1ed1 Boolean, ph\u00e9p to\u00e1n NAND th\u01b0\u1eddng \u0111\u01b0\u1ee3c bi\u1ec3u th\u1ecb b\u1eb1ng k\u00fd hi\u1ec7u \u201c\u2191\u201d.<\/p>\n<h2>C\u1ea5u tr\u00fac b\u00ean trong c\u1ee7a C\u1ed5ng logic NAND. C\u1ed5ng logic NAND ho\u1ea1t \u0111\u1ed9ng nh\u01b0 th\u1ebf n\u00e0o<\/h2>\n<p>C\u1ea5u tr\u00fac b\u00ean trong c\u1ee7a c\u1ed5ng NAND bao g\u1ed3m c\u00e1c b\u00f3ng b\u00e1n d\u1eabn \u0111\u01b0\u1ee3c s\u1eafp x\u1ebfp theo m\u1ed9t c\u1ea5u h\u00ecnh c\u1ee5 th\u1ec3. M\u1ed9t c\u1ed5ng CMOS NAND \u0111i\u1ec3n h\u00ecnh bao g\u1ed3m c\u1ea3 b\u00f3ng b\u00e1n d\u1eabn PMOS (Ch\u1ea5t b\u00e1n d\u1eabn oxit kim lo\u1ea1i lo\u1ea1i P) v\u00e0 NMOS (Ch\u1ea5t b\u00e1n d\u1eabn oxit kim lo\u1ea1i lo\u1ea1i N).<\/p>\n<ol>\n<li>Khi c\u1ea3 hai \u0111\u1ea7u v\u00e0o \u0111\u1ec1u l\u00e0 \u201c1\u201d, c\u00e1c b\u00f3ng b\u00e1n d\u1eabn NMOS d\u1eabn \u0111i\u1ec7n, trong khi c\u00e1c b\u00f3ng b\u00e1n d\u1eabn PMOS th\u00ec kh\u00f4ng. \u0110\u1ea7u ra \u0111\u01b0\u1ee3c n\u1ed1i \u0111\u1ea5t, d\u1eabn \u0111\u1ebfn \u201c0.\u201d<\/li>\n<li>Trong t\u1ea5t c\u1ea3 c\u00e1c tr\u01b0\u1eddng h\u1ee3p kh\u00e1c, b\u00f3ng b\u00e1n d\u1eabn PMOS d\u1eabn \u0111i\u1ec7n, k\u1ebft n\u1ed1i \u0111\u1ea7u ra v\u1edbi ngu\u1ed3n cung c\u1ea5p d\u01b0\u01a1ng, d\u1eabn \u0111\u1ebfn \u201c1\u201d.<\/li>\n<\/ol>\n<h2>Ph\u00e2n t\u00edch c\u00e1c t\u00ednh n\u0103ng ch\u00ednh c\u1ee7a C\u1ed5ng logic NAND<\/h2>\n<ul>\n<li><strong>T\u00ednh ph\u1ed5 qu\u00e1t:<\/strong> C\u1ed5ng NAND c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng \u0111\u1ec3 x\u00e2y d\u1ef1ng b\u1ea5t k\u1ef3 h\u00e0m logic Boolean n\u00e0o.<\/li>\n<li><strong>Hi\u1ec7u qu\u1ea3 n\u0103ng l\u01b0\u1ee3ng:<\/strong> C\u1ed5ng NAND hi\u1ec7n \u0111\u1ea1i \u0111\u01b0\u1ee3c x\u00e2y d\u1ef1ng b\u1eb1ng c\u00f4ng ngh\u1ec7 CMOS gi\u00fap ti\u1ebft ki\u1ec7m n\u0103ng l\u01b0\u1ee3ng.<\/li>\n<li><strong>T\u1ed1c \u0111\u1ed9:<\/strong> C\u1ed5ng NAND th\u01b0\u1eddng nhanh h\u01a1n so v\u1edbi c\u00e1c c\u1ed5ng ph\u1ee9c t\u1ea1p kh\u00e1c.<\/li>\n<li><strong>Kh\u1ea3 d\u1ee5ng:<\/strong> Do t\u00ednh \u0111\u01a1n gi\u1ea3n c\u1ee7a n\u00f3 n\u00ean n\u00f3 \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng r\u1ed9ng r\u00e3i trong c\u00e1c m\u1ea1ch t\u00edch h\u1ee3p.<\/li>\n<\/ul>\n<h2>Vi\u1ebft nh\u1eefng lo\u1ea1i c\u1ed5ng logic NAND t\u1ed3n t\u1ea1i. S\u1eed d\u1ee5ng b\u1ea3ng v\u00e0 danh s\u00e1ch \u0111\u1ec3 vi\u1ebft<\/h2>\n<p>C\u1ed5ng NAND c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c ph\u00e2n lo\u1ea1i d\u1ef1a tr\u00ean s\u1ed1 l\u01b0\u1ee3ng \u0111\u1ea7u v\u00e0o, c\u00f4ng ngh\u1ec7 \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng ho\u1eb7c c\u00e1c t\u00ednh n\u0103ng c\u1ee5 th\u1ec3 kh\u00e1c:<\/p>\n<table>\n<thead>\n<tr>\n<th>Ki\u1ec3u<\/th>\n<th>S\u1ef1 mi\u00eau t\u1ea3<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>NAND 2 \u0111\u1ea7u v\u00e0o<\/td>\n<td>C\u1ed5ng NAND hai \u0111\u1ea7u v\u00e0o ti\u00eau chu\u1ea9n<\/td>\n<\/tr>\n<tr>\n<td>NAND 3 \u0111\u1ea7u v\u00e0o<\/td>\n<td>Nh\u1eadn ba \u0111\u1ea7u v\u00e0o, ch\u1ec9 xu\u1ea5t ra 1 n\u1ebfu t\u1ea5t c\u1ea3 \u0111\u1ea7u v\u00e0o b\u1eb1ng 0<\/td>\n<\/tr>\n<tr>\n<td>NAND 4 \u0111\u1ea7u v\u00e0o<\/td>\n<td>Nh\u1eadn b\u1ed1n \u0111\u1ea7u v\u00e0o, ho\u1ea1t \u0111\u1ed9ng t\u01b0\u01a1ng t\u1ef1 nh\u01b0 tr\u00ean<\/td>\n<\/tr>\n<tr>\n<td>CMOS NAND<\/td>\n<td>\u0110\u01b0\u1ee3c x\u00e2y d\u1ef1ng b\u1eb1ng c\u00f4ng ngh\u1ec7 MOSFET b\u1ed5 sung<\/td>\n<\/tr>\n<tr>\n<td>TTL NAND<\/td>\n<td>\u0110\u01b0\u1ee3c x\u00e2y d\u1ef1ng b\u1eb1ng logic Transistor-Transistor<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>C\u00e1ch s\u1eed d\u1ee5ng C\u1ed5ng logic NAND, c\u00e1c v\u1ea5n \u0111\u1ec1 v\u00e0 gi\u1ea3i ph\u00e1p li\u00ean quan \u0111\u1ebfn vi\u1ec7c s\u1eed d\u1ee5ng<\/h2>\n<p>C\u1ed5ng NAND \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng r\u1ed9ng r\u00e3i trong nhi\u1ec1u \u1ee9ng d\u1ee5ng kh\u00e1c nhau:<\/p>\n<ul>\n<li><strong>H\u1ec7 th\u1ed1ng k\u1ef9 thu\u1eadt s\u1ed1:<\/strong> Kh\u1ed1i x\u00e2y d\u1ef1ng cho c\u00e1c m\u1ea1ch k\u1ef9 thu\u1eadt s\u1ed1 ph\u1ee9c t\u1ea1p.<\/li>\n<li><strong>C\u00e1c ph\u00e9p t\u00ednh to\u00e1n h\u1ecdc:<\/strong> \u0110\u01b0\u1ee3c s\u1eed d\u1ee5ng trong c\u00e1c \u0111\u01a1n v\u1ecb logic s\u1ed1 h\u1ecdc (ALU).<\/li>\n<li><strong>\u0110\u01a1n v\u1ecb b\u1ed9 nh\u1edb:<\/strong> \u0110\u01b0\u1ee3c s\u1eed d\u1ee5ng trong c\u00e1c thi\u1ebft b\u1ecb l\u01b0u tr\u1eef nh\u01b0 RAM v\u00e0 ROM.<\/li>\n<li><strong>V\u1ea5n \u0111\u1ec1 v\u00e0 gi\u1ea3i ph\u00e1p:<\/strong>\n<ul>\n<li><strong>\u0110\u1ed9 nh\u1ea1y c\u1ea3m v\u1edbi ti\u1ebfng \u1ed3n:<\/strong> Thi\u1ebft k\u1ebf che ch\u1eafn v\u00e0 h\u1ea1n ch\u1ebf ti\u1ebfng \u1ed3n ph\u00f9 h\u1ee3p.<\/li>\n<li><strong>S\u1ef1 ti\u00eau th\u1ee5 n\u0103ng l\u01b0\u1ee3ng:<\/strong> S\u1eed d\u1ee5ng c\u00f4ng ngh\u1ec7 CMOS hi\u1ec7n \u0111\u1ea1i gi\u00fap gi\u1ea3m \u0111i\u1ec7n n\u0103ng.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<h2>C\u00e1c \u0111\u1eb7c \u0111i\u1ec3m ch\u00ednh v\u00e0 nh\u1eefng so s\u00e1nh kh\u00e1c v\u1edbi c\u00e1c thu\u1eadt ng\u1eef t\u01b0\u01a1ng t\u1ef1 \u1edf d\u1ea1ng b\u1ea3ng v\u00e0 danh s\u00e1ch<\/h2>\n<table>\n<thead>\n<tr>\n<th>\u0111\u1eb7c tr\u01b0ng<\/th>\n<th>NAND<\/th>\n<th>V\u00c0<\/th>\n<th>HO\u1eb6C<\/th>\n<th>C\u0168NG KH\u00d4NG<\/th>\n<\/tr>\n<\/thead>\n<tbody>\n<tr>\n<td>\u0111\u1ea7u ra<\/td>\n<td>0 n\u1ebfu c\u1ea3 hai \u0111\u1ea7u v\u00e0o l\u00e0 1<\/td>\n<td>1 n\u1ebfu c\u1ea3 hai \u0111\u1ea7u v\u00e0o l\u00e0 1<\/td>\n<td>1 n\u1ebfu b\u1ea5t k\u1ef3 \u0111\u1ea7u v\u00e0o n\u00e0o l\u00e0 1<\/td>\n<td>0 n\u1ebfu b\u1ea5t k\u1ef3 \u0111\u1ea7u v\u00e0o n\u00e0o l\u00e0 1<\/td>\n<\/tr>\n<tr>\n<td>T\u00ednh ph\u1ed5 qu\u00e1t<\/td>\n<td>\u0110\u00fang<\/td>\n<td>KH\u00d4NG<\/td>\n<td>KH\u00d4NG<\/td>\n<td>KH\u00d4NG<\/td>\n<\/tr>\n<tr>\n<td>\u0110\u1ed9 ph\u1ee9c t\u1ea1p<\/td>\n<td>Th\u1ea5p<\/td>\n<td>Th\u1ea5p<\/td>\n<td>Th\u1ea5p<\/td>\n<td>Th\u1ea5p<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Quan \u0111i\u1ec3m v\u00e0 c\u00f4ng ngh\u1ec7 c\u1ee7a t\u01b0\u01a1ng lai li\u00ean quan \u0111\u1ebfn C\u1ed5ng logic NAND<\/h2>\n<p>C\u1ed5ng NAND ti\u1ebfp t\u1ee5c l\u00e0 m\u1ed9t th\u00e0nh ph\u1ea7n quan tr\u1ecdng trong c\u00f4ng ngh\u1ec7 ti\u00ean ti\u1ebfn. V\u1edbi s\u1ef1 ph\u00e1t tri\u1ec3n c\u1ee7a \u0111i\u1ec7n to\u00e1n l\u01b0\u1ee3ng t\u1eed, \u0111i\u1ec7n to\u00e1n quang h\u1ecdc v\u00e0 c\u00f4ng ngh\u1ec7 nano, c\u00e1c lo\u1ea1i c\u1ed5ng NAND m\u1edbi d\u1ef1 ki\u1ebfn s\u1ebd xu\u1ea5t hi\u1ec7n th\u1eadm ch\u00ed c\u00f2n nhanh h\u01a1n v\u00e0 ti\u1ebft ki\u1ec7m n\u0103ng l\u01b0\u1ee3ng h\u01a1n.<\/p>\n<h2>C\u00e1ch s\u1eed d\u1ee5ng ho\u1eb7c li\u00ean k\u1ebft m\u00e1y ch\u1ee7 proxy v\u1edbi C\u1ed5ng logic NAND<\/h2>\n<p>M\u00e1y ch\u1ee7 proxy qu\u1ea3n l\u00fd v\u00e0 l\u1ecdc lu\u1ed3ng d\u1eef li\u1ec7u, th\u01b0\u1eddng d\u1ef1a v\u00e0o c\u00e1c c\u1ed5ng logic nh\u01b0 NAND trong ki\u1ebfn tr\u00fac ph\u1ea7n c\u1ee9ng c\u01a1 b\u1ea3n c\u1ee7a ch\u00fang. B\u1eb1ng c\u00e1ch t\u1ed1i \u01b0u h\u00f3a vi\u1ec7c s\u1eed d\u1ee5ng c\u1ed5ng NAND trong x\u1eed l\u00fd d\u1eef li\u1ec7u, c\u00e1c m\u00e1y ch\u1ee7 proxy nh\u01b0 OneProxy c\u00f3 th\u1ec3 qu\u1ea3n l\u00fd d\u1eef li\u1ec7u nhanh h\u01a1n v\u00e0 an to\u00e0n h\u01a1n. T\u00ednh ph\u1ed5 qu\u00e1t c\u1ee7a c\u1ed5ng NAND \u0111\u00f3ng m\u1ed9t vai tr\u00f2 quan tr\u1ecdng trong hi\u1ec7u su\u1ea5t m\u1ea1nh m\u1ebd v\u00e0 th\u00edch \u1ee9ng c\u1ee7a c\u00e1c h\u1ec7 th\u1ed1ng n\u00e0y.<\/p>\n<h2>Li\u00ean k\u1ebft li\u00ean quan<\/h2>\n<ol>\n<li><a href=\"https:\/\/ieeexplore.ieee.org\" target=\"_new\" rel=\"noopener nofollow\">IEEE Xplore \u2013 C\u00f4ng ngh\u1ec7 c\u1ed5ng NAND<\/a><\/li>\n<li><a href=\"https:\/\/en.wikipedia.org\/wiki\/NAND_gate\" target=\"_new\" rel=\"noopener nofollow\">Wikipedia \u2013 C\u1ed5ng NAND<\/a><\/li>\n<li><a href=\"https:\/\/oneproxy.pro\/vn\/\" target=\"_new\" rel=\"noopener\">Trang web ch\u00ednh th\u1ee9c c\u1ee7a OneProxy<\/a><\/li>\n<li><a href=\"https:\/\/www.computerhistory.org\" target=\"_new\" rel=\"noopener nofollow\">B\u1ea3o t\u00e0ng L\u1ecbch s\u1eed M\u00e1y t\u00ednh \u2013 Claude Shannon<\/a><\/li>\n<\/ol>","protected":false},"featured_media":468977,"menu_order":0,"template":"","meta":{"_acf_changed":false,"content-type":"","inline_featured_image":false,"footnotes":""},"class_list":["post-478094","wiki","type-wiki","status-publish","has-post-thumbnail","hentry"],"acf":{"faq_title":"Frequently Asked Questions about <mark>NAND Logic Gate<\/mark>","faq_items":[{"question":"What is a NAND Logic Gate?","answer":"<p>A NAND logic gate is a digital logic gate that outputs false or \"0\" only when both its inputs are true or \"1.\" In all other cases, it returns true or \"1.\" It's one of the fundamental building blocks in digital electronics, known for its universality in constructing any Boolean logic function.<\/p>"},{"question":"How Does a NAND Logic Gate Work?","answer":"<p>A NAND gate consists of transistors arranged in a specific configuration. When both inputs are \"1,\" the output is \"0.\" In all other cases, the output is \"1.\" The typical CMOS NAND gate uses both PMOS and NMOS transistors to achieve this functionality.<\/p>"},{"question":"What are the Key Features of a NAND Logic Gate?","answer":"<p>The key features of a NAND logic gate include its universality in constructing any Boolean logic function, energy efficiency, speed, and wide availability in integrated circuits.<\/p>"},{"question":"What Types of NAND Logic Gates Exist?","answer":"<p>NAND gates can be classified based on the number of inputs or technology used, such as 2-input, 3-input, 4-input NAND gates, and those built using CMOS or Transistor-Transistor Logic (TTL).<\/p>"},{"question":"Where are NAND Logic Gates Used?","answer":"<p>NAND gates are used extensively in digital systems, arithmetic logic units (ALUs), and memory units like RAM and ROM. They serve as building blocks for complex digital circuits.<\/p>"},{"question":"What Problems Might Be Associated with the Use of NAND Logic Gates, and How Can They Be Solved?","answer":"<p>Some problems related to the use of NAND gates include noise susceptibility and power consumption. Solutions include proper shielding and noise margin design, and using modern CMOS technology to reduce power.<\/p>"},{"question":"How Are NAND Logic Gates Relevant to Proxy Servers Like OneProxy?","answer":"<p>Proxy servers like OneProxy manage and filter data flow, relying on logic gates like NAND in their underlying hardware architecture. NAND gates play a vital role in the adaptable and robust performance of these systems.<\/p>"},{"question":"What Are the Future Perspectives Related to NAND Logic Gates?","answer":"<p>With advancements in quantum computing, optical computing, and nanotechnology, new types of NAND gates are expected to emerge that are even faster and more energy-efficient.<\/p>"},{"question":"How Can I Learn More About NAND Logic Gates?","answer":"<p>You can learn more about NAND logic gates by visiting resources like <a href=\"https:\/\/ieeexplore.ieee.org\" target=\"_new\">IEEE Xplore - NAND Gate Technology<\/a>, <a href=\"https:\/\/en.wikipedia.org\/wiki\/NAND_gate\" target=\"_new\">Wikipedia - NAND Gate<\/a>, and <a href=\"https:\/\/www.computerhistory.org\" target=\"_new\">Computer History Museum - Claude Shannon<\/a>.<\/p>"}]},"_links":{"self":[{"href":"https:\/\/oneproxy.pro\/vn\/wp-json\/wp\/v2\/wiki\/478094","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/oneproxy.pro\/vn\/wp-json\/wp\/v2\/wiki"}],"about":[{"href":"https:\/\/oneproxy.pro\/vn\/wp-json\/wp\/v2\/types\/wiki"}],"version-history":[{"count":0,"href":"https:\/\/oneproxy.pro\/vn\/wp-json\/wp\/v2\/wiki\/478094\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/oneproxy.pro\/vn\/wp-json\/wp\/v2\/media\/468977"}],"wp:attachment":[{"href":"https:\/\/oneproxy.pro\/vn\/wp-json\/wp\/v2\/media?parent=478094"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}